The present invention relates to a semiconductor device, and more particularly to a ball grid array semiconductor device.
In prior art, semiconductor chips are sealed with a resin material or a ceramic material to form a semiconductor package, wherein lead frames are connected to the semiconductor chips and external leads are projected from the semiconductor package, whereby the external leads are solder-bonded to a mounting substrate such as a printed board. This traditional semiconductor device using lead frames requires a large mounting area, making it difficult to scale down the semiconductor device. Recently, a ball grid array semiconductor device has been used which is suitable for reducing mounting area by using grid arrays of solder balls in place of using lead frames. Namely, the ball grid array semiconductor device more suitable for high density packaging than are traditional lead frame semiconductor devices.
FIG. 1A is a plan view illustrative of a conventional land structure for a solder ball in the ball grid array of the ball grid array semiconductor device. FIG. 1B is a cross sectional elevation view illustrative of the conventional land structure for the solder ball in the ball grid array of the ball grid array semiconductor device, taken along an IB-IB, line of FIG. 1A.
A land 2 is formed in a packaging portion 7, wherein the land 2 comprises a circular-shaped recessed portion 8 which has a slightly larger size than a solder ball 1 for receipt of the solder ball 1. Normally, the solder ball 1 is dipped in a flux 3 before placed within the land 2, wherein the flux 3 exists between the solder ball 1 and the land 2. Since, as described above, the land 2 comprises the circular-shaped recessed portion 8 which has the slightly larger size than a solder ball 1, the flux 3 is confined in an extremely narrow space defined between the solder ball 1 and the land 2, whereby the flux 3 floats the solder ball 1 from the land 2, resulting in an electrical disconnection of the solder ball 1 from the land 2.
In Japanese laid-open patent publication No. 64-16637, it is disclosed that, as illustrated in FIG. 2, a solder-flow pattern 5 is formed to permit any excess amount of solder to flow through the solder-flow pattern 5 serving as a flow channel. This conventional technique, however, does solve the problem of the excess flux floating the solder ball off the land.
In the above circumstances, it had been required to develop a novel land structure which makes the ball grid array semiconductor device free from the above problems with the floating of the solder ball from the land by the excess amount of the flux.